ADZS-21371-EZLITE【PDF 10/56 页】KIT EVAL EZLITE ADZS-21371

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ADSP-21371 / ADSP-21375

DMA channels, one for transmit and one for receive. These

DMA channels have lower default priority than most DMA

channels because of their relatively low service rates.

port (PDAP), or the UART (see Table 7 ).

Table 7. DMA Channels

The UART port’s baud rate, serial data format, error code gen-

eration and status, and interrupts are programmable. The port:

? Supports bit rates ranging from (f PCLK /1,048,576) to

(f PCLK /16) bits per second.

? Supports data formats from 7 to 12 bits per frame.

? Can be configured to generate maskable interrupts for both

transmit and receive operations.

In conjunction with the general-purpose timer functions, auto-

baud detection is supported.

Peripheral

SPORT

PDAP

SPI

UART

EP

MTM/DTCP

Total DMA Channels

ADSP-21371

16

8

2

2

2

2

32

ADSP-21375

8

8

2

2

2

2

24

Peripheral Timers

Two general-purpose timers can generate periodic interrupts

and be independently set to operate in one of three modes:

? Pulse waveform generation mode

? Pulse width count/capture mode

? External event watchdog mode

Each general-purpose timer has one bidirectional pin and four

registers that implement its mode of operation: a 6-bit configu-

ration register, a 32-bit count register, a 32-bit period register,

and a 32-bit pulse width register. A single control and status

register enables or disables the general-purpose timers

independently.

2-Wire Interface Port (TWI)

The TWI is a bidirectional 2-wire serial bus used to move 8-bit

data while maintaining compliance with the I 2 C bus protocol.

The TWI master incorporates the following features:

? Simultaneous master and slave operation on multiple

device systems with support for multi master data

arbitration

? Digital filtering and timed event processing

? 7-bit addressing

? 100 kbps and 400 kbps data rates

Delay Line DMA

The processors provide delay line DMA functionality. This

allows processor reads and writes to external delay line buffers

(and hence to external memory) with limited core interaction.

Scatter/Gather DMA

The ADSP-2137x processor provides scatter/gather DMA func-

tionality. This allows processor DMA reads/writes to/from non-

contiguous memory blocks.

SYSTEM DESIGN

The following sections provide an introduction to system design

options and power supply issues. For complete system design

information, see the ADSP-2137x SHARC Processor Hardware

Reference .

Program Booting

The internal memory of the processor boots at system power-up

from an 8-bit EPROM via the external port, an SPI master, or an

SPI slave. Booting is determined by the boot configuration

(BOOT_CFG1–0) pins in Table 8 . Selection of the boot source

is controlled via the SPI as either a master or slave device, or it

can immediately begin executing from ROM.

Table 8. Boot Mode Selection

? Low interrupt rate

I/O PROCESSOR FEATURES

The I/O processor provides many channels of DMA and con-

trols the extensive set of peripherals described in the previous

BOOT_CFG1–0

00

01

10

11

Booting Mode

SPI Slave Boot

SPI Master Boot

EPROM/FLASH Boot

No boot (processor executes from

sections.

DMA Controller

The processor’s on-chip DMA controller allows data transfers

without processor intervention. The DMA controller operates

independently and invisibly to the processor core, allowing

internal ROM after reset)

The “Running Reset” feature allows programs to perform a reset

of the processor core and peripherals, but without resetting the

PLL and SDRAM controller, or performing a boot. The RESET-

OUT pin acts as the input for initiating a running reset.

DMA operations to occur while the core is simultaneously exe-

cuting its program instructions. DMA transfers can occur

between the ADSP-2137x processor’s internal memory and its

serial ports, the SPI-compatible (serial peripheral interface)

ports, the IDP (input data port), the parallel data acquisition

Rev. D | Page 10 of 56 | April 2013

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